AS7C34096-20TI 查看數據表（PDF） - Alliance Semiconductor
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AS7C34096-20TI Datasheet PDF : 9 Pages
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AS7C4096
AS7C34096
®
AC test conditions
- Output load: see Figure B or Figure C.
- Input pulse level: GND to 3.0V. See Figures A, B, and C.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
+5V
Thevenin equivalent:
168Ω
DOUT
+1.728V
+3.3V
+3.0V
90%
90%
10%
10%
GND
2 ns
Figure A: Input pulse
DOUT
255Ω
480Ω
C13
GND
Figure B: 5V Output load
DOUT
350Ω
320Ω
C13
GND
Figure C: 3.3V Output load
Notes
1 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions.
4 tCLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500 mV from steady-state voltage.
5 This parameter is guaranteed, but not tested.
6 WE is HIGH for read cycle.
7 CE and OE are LOW for read cycle.
8 Address valid prior to or coincident with CE transition Low.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE or WE must be HIGH during address transitions. Either CE or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 Not applicable.
13 C = 30pF, except at high Z and low Z parameters, where C = 5pF.
1/13/05; v.1.9
Alliance Semiconductor
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