M48Z32V-35MT1E(2007) 查看數據表（PDF） - STMicroelectronics
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M48Z32V-35MT1E Datasheet PDF : 19 Pages
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M48Z32V
2
Operating modes
Operating modes
Note:
2.1
The M48Z32V also has its own Power-fail Detect circuit. The control circuitry constantly
monitors the single power supply for an out of tolerance condition. When VCC is out of
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low VCC. As VCC falls below
approximately VSO, the control circuitry connects the battery which maintains data until valid
power returns.
Table 2. Operating modes
Mode
VCC
E
G
W
Deselect
VIH
X
X
WRITE
READ
3.0 to 3.6V
VIL
X
VIL
VIL
VIL
VIH
READ
VIL
VIH
VIH
Deselect
VSO to VPFD (min)(1)
X
X
X
Deselect
≤ VSO(1)
X
X
X
1. See Table 12 on page 15 for details.
X = VIH or VIL; VSO = Battery back-up switchover voltage.
DQ0-DQ7
High Z
DIN
DOUT
High Z
High Z
High Z
Power
Standby
Active
Active
Active
CMOS standby
Battery back-up
mode
Read mode
The M48Z32V is in the READ Mode whenever W (WRITE Enable) is high, E (Chip Enable)
is low. The device architecture allows ripple-through access of data from eight of 262,144
locations in the static storage array. Thus, the unique address specified by the 15 Address
Inputs defines which one of the 32,768 bytes of data is to be accessed. Valid data will be
available at the Data I/O pins within Address Access time (tAVQV) after the last address input
signal is stable, providing that the E and G access times are also satisfied. If the E and G
access times are not met, valid data will be available after the latter of the Chip Enable
Access time (tELQV) or Output Enable Access time (tGLQV).
The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are
activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If
the Address Inputs are changed while E and G remain active, output data will remain valid
for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access.
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