M48Z32VMT(2007) 查看數據表（PDF） - STMicroelectronics
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M48Z32VMT Datasheet PDF : 19 Pages
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Operating modes
M48Z32V
Figure 4. Read mode AC waveforms
A0-A14
tAVAV
VALID
tAVQV
tELQV
E
tELQX
tGLQV
G
DQ0-DQ7
tGLQX
tAXQX
tEHQZ
tGHQZ
VALID
AI00925
Note:
WRITE Enable (W) = High.
Table 3. Read mode AC characteristics
Symbol
Parameter(1)
M48Z32V
–35
Min
tAVAV
READ cycle time
35
tAVQV
Address valid to output valid
tELQV
Chip enable low to output valid
tGLQV
Output enable low to output valid
tELQX(2)
Chip enable low to output transition
5
tGLQX(2)
Output enable low to output transition
0
tEHQZ(2)
Chip enable high to output Hi-Z
tGHQZ(2)
Output enable high to output Hi-Z
tAXQX
Address transition to output transition
5
1. Valid for ambient operating temperature: TA = 0 to 70°C; Vcc = 3.0 to 3.6V (except where noted).
2. CL = 5pf (see Figure 8 on page 16).
Max
35
35
15
13
13
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.2
Write mode
The M48Z32V is in the WRITE Mode whenever W and E are low. The start of a WRITE is
referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the
earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W
must return high for a minimum of tEHAX from Chip Enable or tWHAX from WRITE Enable
prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to
the end of WRITE and remain valid for tWHDX afterward. G should be kept high during
WRITE cycles to avoid bus contention; although, if the output bus has been activated by a
low on E and G, a low on W will disable the outputs tWLQZ after W falls.
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