M48Z32V 查看數據表（PDF） - STMicroelectronics
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M48Z32V Datasheet PDF : 16 Pages
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M48Z32V
READ Mode
The M48Z32V is in the READ Mode whenever W
(WRITE Enable) is high, E (Chip Enable) is low.
The device architecture allows ripple-through ac-
cess of data from eight of 262,144 locations in the
static storage array. Thus, the unique address
specified by the 15 Address Inputs defines which
one of the 32,768 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (tAVQV) after the last
address input signal is stable, providing that the E
and G access times are also satisfied. If the E and
G access times are not met, valid data will be
available after the latter of the Chip Enable Access
time (tELQV) or Output Enable Access time
(tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address In-
puts are changed while E and G remain active,
output data will remain valid for Output Data Hold
time (tAXQX) but will go indeterminate until the next
Address Access.
Figure 5. READ Mode AC Waveforms
A0-A14
tAVAV
VALID
tAVQV
tELQV
E
tELQX
tGLQV
G
DQ0-DQ7
tGLQX
tAXQX
tEHQZ
tGHQZ
VALID
Note: WRITE Enable (W) = High.
AI00925
Table 3. READ Mode AC Characteristics
M48Z32V
Symbol
Parameter(1)
–35
Min Max
tAVAV
READ Cycle Time
35
tAVQV
Address Valid to Output Valid
35
tELQV
Chip Enable Low to Output Valid
35
tGLQV
Output Enable Low to Output Valid
15
tELQX(2)
Chip Enable Low to Output Transition
5
tGLQX(2)
Output Enable Low to Output Transition
0
tEHQZ(2)
Chip Enable High to Output Hi-Z
13
tGHQZ(2)
Output Enable High to Output Hi-Z
13
tAXQX
Address Transition to Output Transition
5
0
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 3.0 to 3.6V (except where noted).
2. CL = 5pF (see Figure 9., page 10).
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
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