C167CR-16F 查看數據表（PDF） - Siemens AG
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C167CR-16F Datasheet PDF : 63 Pages
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C167CR-16F
06May97@14:10h Intermediate Version
In order not to exceed the limit values listed above, a specific CKCTL setting requires a minimum
CPU clock frequency, as listed below.
Setting of
CKCTL
00
01
10
11
Length of
TPRG
28 * 1/fCPU
211 * 1/fCPU
215 * 1/fCPU
218 * 1/fCPU
TPRG
@ fCPU = 20 MHz
12.8 µs
fCPUmin
for programming
1.28 MHz
102.4 µs
10.24 MHz
1.64 ms
---
13.11 ms
---
fCPUmin
for erasing
( 12.8 KHz ) 1)
( 102.4 KHz ) 1)
1.64 MHz
13.11 MHz
1) Please note that these are computed values. Actual values must respect the operational range
specified for the C167CR-16F.
The maximum number of allowed programming or erase attempts depends on the CPU clock
frequency and on the CKCTL setting chosen in turn. This number results from the actual pulse width
compared to the maximum pulse width (see above tables).
The table below lists some sample frequencies, the respective recommended CKCTL setting and
the resulting maximum number of program / erase pulses:
fCPU
1 MHz
10 MHz
16 MHz
20 MHz
CKCTL
00
00
00
00
Programming
TPROG
128 µs
NPROGmax
19
12.8 µs
195
8 µs
312
6.4 µs
390
CKCTL
01
10
10
10
Erasing
TPROG
2.05 ms
3.28 ms
2.05 ms
1.64 ms
NERASEmax
14648
9155
14648
18310
BE: The Flash Bank Erasing bit field determines the Flash memory bank to be erased (see table
below). The physical addresses of the lower 32 KBytes of bank 0 depend on the Flash memory
mapping chosen.
BE setting
00
01
10
11
Bank
0
1
2
3
Size
48 KB
48 KB
24 KB
8 KB
Addresses Selected for Erasure (x = 0 or 1)
0x’0000H to 0x’7FFFH / 01’8000H to 01’BFFFH
01’C000H to 01’FFFFH / 02’0000H to 02’7FFFH
02’8000H to 02’DFFFH
02’E000H to 02’FFFFH
Semiconductor Group
16
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