ACE9050IG 查看數據表（PDF） - Mitel Networks
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ACE9050IG Datasheet PDF : 52 Pages
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TIMING DIAGRAMS
ACE9050
NORMAL MODE PROCESSOR INTERFACE
Read Cycle
ECLK
tECLK
ADDR
CS
OEN
DATA
tADVCSL
tCSLCLL
tOELCLL
tDAVCLL
tCLLADI
tCLLCSH
tCLLOEH
tCLLDAI
Fig.4 ACE9050 6303 Read cycle timing diagram
Timing Cycle Conditions
Input clock frequency, XIN = 8·064MHz. Worst case Timings: TAMB = 240°C to 185°C, VDD = 13·6V to 15·5V
Typical timings: TAMB = 125°C, VDD = 13·75V
Description
Symbol
Normal clock
Min.
Typ. Max.
Turbo clock
Min.
Typ.
Max.
Cycle time
Address valid to CS low
Chip Select set-up time
OEN set-up time
Data set-up time
Data hold time
OEN hold time
CS hold time
Address hold time
tECLK
tADVCSL
tCSLCLL
tOELCLL
tDAVCLL
tCLLDAI
tCLLOEH
tCLLCSH
tCLLADI
992
2
4
9
2
940
972
985
445
485
492
495
240
35
35
0
0
0
1
4
0
9
24
45
9
7
18
42
7
Table 3 ACE9050 6303 Read cycle timing
496
4
9
480
490
245
248
1
4
24
45
18
42
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
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