C8051F000 查看數據表（PDF） - Unspecified
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C8051F000 Datasheet PDF : 170 Pages
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PRELIMINARY
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
1.1. CIP-51TM CPU
1.1.1. Fully 8051 Compatible
The C8051F000 family utilizes Cygnal’s proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible
with the MCS-51TM instruction set. Standard 803x/805x assemblers and compilers can be used to develop software.
The core has all the peripherals included with a standard 8052, including four 16-bit counter/timers, a full-duplex
UART, 256 bytes of internal RAM space, 128 byte Special Function Register (SFR) address space, and four byte-
wide I/O Ports.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051
architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to
execute with a maximum system clock of 12-to-24MHz. By contrast, the CIP-51 core executes 70% of its
instructions in one or two system clock cycles, with only four instructions taking more than four system clock cycles.
The CIP-51 has a total of 109 instructions. The number of instructions versus the system clock cycles to execute
them is as follows:
Instructions 26
50
5
14
7
3
1
2
1
Clocks to Execute 1
2
2/3
3
3/4
4
4/5
5
8
With the CIP-51’s maximum system clock at 25MHz, it has a peak throughput of 25MIPS. Figure 1.4 shows a
comparison of peak throughputs of various 8-bit microcontroller cores with their maximum system clocks.
Figure 1.4. Comparison of Peak MCU Execution Speeds
25
20
15
10
5
Cygnal Microchip Philips ADuC812
CIP-51 PIC17C75x 80C51
8051
(25MHz clk) (33MHz clk) (33MHz clk) (16MHz clk)
Page 12
CYGNAL Integrated Products, Inc. 2001
4.2001; Rev. 1.3
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