C8051F000 查看數據表（PDF） - Unspecified

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C8051F000

Mixed-Signal 32KB ISP FLASH MCU Family

Unspecified 

PRELIMINARY

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

1.7. Analog to Digital Converter

The C8051F000/1/2/5/6/7 has an on-chip 12-bit SAR ADC with a 9-channel input multiplexer and programmable

gain amplifier. With a maximum throughput of 100ksps, the ADC offers true 12-bit accuracy with an INL of ±1LSB.

The ADC in the C8051F010/1/2/5/6/7 is similar, but with 10-bit resolution. Each ADC has a maximum throughput

of 100ksps. Each ADC has an INL of ±1LSB, offering true 12-bit accuracy with the C8051F00x, and true 10-bit

accuracy with the C8051F01x. There is also an on-board 15ppm voltage reference, or an external reference may be

used via the VREF pin.

The ADC is under full control of the CIP-51 microcontroller via the Special Function Registers. One input channel

is tied to an internal temperature sensor, while the other eight channels are available externally. Each pair of the

eight external input channels can be configured as either two single-ended inputs or a single differential input. The

system controller can also put the ADC into shutdown to save power.

A programmable gain amplifier follows the analog multiplexer. The gain can be set in software from 0.5 to 16 in

powers of 2. The gain stage can be especially useful when different ADC input channels have widely varied input

voltage signals, or when it is necessary to “zoom in” on a signal with a large DC offset (in differential mode, a DAC

could be used to provide the DC offset).

Conversions can be started in four ways; a software command, an overflow on Timer 2, an overflow on Timer 3, or

an external signal input. This flexibility allows the start of conversion to be triggered by software events, external

HW signals, or convert continuously. A completed conversion causes an interrupt, or a status bit can be polled in

software to determine the end of conversion. The resulting 10 or 12-bit data word is latched into two SFRs upon

completion of a conversion. The data can be right or left justified in these registers under software control.

Compare registers for the ADC data can be configured to interrupt the controller when ADC data is within a

specified window. The ADC can monitor a key voltage continuously in background mode, but not interrupt the

controller unless the converted data is within the specified window.

Figure 1.10. ADC Diagram

VREF

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

(not bonded out on

F002, F007, F012,

and F017

+

-

+

- 9-to-1

+

AMUX

(SE or

- DIFF)

+

-

Programmable

Gain Amp

X

+

-

TEMP

SENSOR

REF

100ksps

SAR

ADC

Page 18

Control & Data

SFR's

CYGNAL Integrated Products, Inc.  2001

SFR Bus

4.2001; Rev. 1.3

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