C8051F015 查看數據表（PDF） - Silicon Laboratories
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C8051F015 Datasheet PDF : 171 Pages
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C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 10.5. DPH: Data Pointer High Byte .....................................................................................................74
Figure 10.6. PSW: Program Status Word........................................................................................................75
Figure 10.7. ACC: Accumulator......................................................................................................................76
Figure 10.8. B: B Register ...............................................................................................................................76
10.4. INTERRUPT HANDLER .................................................................................................................77
Table 10.4. Interrupt Summary........................................................................................................................78
Figure 10.9. IE: Interrupt Enable.....................................................................................................................79
Figure 10.10. IP: Interrupt Priority..................................................................................................................80
Figure 10.11. EIE1: Extended Interrupt Enable 1 ...........................................................................................81
Figure 10.12. EIE2: Extended Interrupt Enable 2 ...........................................................................................82
Figure 10.13. EIP1: Extended Interrupt Priority 1 ..........................................................................................83
Figure 10.14. EIP2: Extended Interrupt Priority 2 ..........................................................................................84
10.5. Power Management Modes ...............................................................................................................85
Figure 10.15. PCON: Power Control Register ................................................................................................86
11. FLASH MEMORY.............................................................................................................87
11.1. Programming The Flash Memory......................................................................................................87
Table 11.1. FLASH Memory Electrical Characteristics ..................................................................................87
11.2. Non-volatile Data Storage .................................................................................................................88
11.3. Security Options ................................................................................................................................88
Figure 11.1. PSCTL: Program Store RW Control...........................................................................................88
Figure 11.2. Flash Program Memory Security Bytes .......................................................................................89
Figure 11.3. FLACL: Flash Access Limit (C8051F005/06/07/15/16/17 only) ...............................................90
Figure 11.4. FLSCL: Flash Memory Timing Prescaler ...................................................................................91
12. EXTERNAL RAM (C8051F005/06/07/15/16/17).............................................................92
Figure 12.1. EMI0CN: External Memory Interface Control ...........................................................................92
13. RESET SOURCES .............................................................................................................93
Figure 13.1. Reset Sources Diagram ...............................................................................................................93
13.1. Power-on Reset..................................................................................................................................94
13.2. Software Forced Reset.......................................................................................................................94
Figure 13.2. VDD Monitor Timing Diagram ..................................................................................................94
13.3. Power-fail Reset.................................................................................................................................94
13.4. External Reset....................................................................................................................................95
13.5. Missing Clock Detector Reset ...........................................................................................................95
13.6. Comparator 0 Reset ...........................................................................................................................95
13.7. External CNVSTR Pin Reset.............................................................................................................95
13.8. Watchdog Timer Reset ......................................................................................................................95
Figure 13.3. WDTCN: Watchdog Timer Control Register .............................................................................96
Figure 13.4. RSTSRC: Reset Source Register.................................................................................................97
Table 13.1. Reset Electrical Characteristics ....................................................................................................98
14. OSCILLATOR ...................................................................................................................99
Figure 14.1. Oscillator Diagram ......................................................................................................................99
Figure 14.2. OSCICN: Internal Oscillator Control Register .........................................................................100
Table 14.1. Internal Oscillator Electrical Characteristics ..............................................................................100
Figure 14.3. OSCXCN: External Oscillator Control Register.......................................................................101
14.1. External Crystal Example ................................................................................................................102
14.2. External RC Example ......................................................................................................................102
14.3. External Capacitor Example ............................................................................................................102
15. PORT INPUT/OUTPUT..................................................................................................103
15.1. Priority Cross Bar Decoder..............................................................................................................103
15.2. Port I/O Initialization.......................................................................................................................103
Figure 15.1. Port I/O Functional Block Diagram ..........................................................................................104
Figure 15.2. Port I/O Cell Block Diagram.....................................................................................................104
Table 15.1. Crossbar Priority Decode ...........................................................................................................105
Figure 15.3. XBR0: Port I/O CrossBar Register 0 ........................................................................................106
Rev. 1.7
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