C8051F000 查看數據表（PDF） - Silicon Laboratories

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C8051F000

Mixed-Signal 32KB ISP FLASH MCU Family

Silicon Laboratories 

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

VDD

VDD

VDD

DGND

DGND

DGND

AV+

AV+

AGND

AGND

TCK

TMS

TDI

TDO

/RST

XTAL1

XTAL2

VREF

DAC0

DAC1

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

CP0+

CP0-

CP1+

CP1-

Figure 1.1. C8051F000/05/10/15 Block Diagram

Digital Power

C

UART

R

SMBus

O

Analog Power

SPI Bus

S

PCA

S

B

JTAG Boundary Scan

8

Logic Debug HW

0

Reset

5

32kbyte

FLASH

256 byte

RAM

Timers

A

0,1,2

R

Timer 3

Port 0

S

Latch

W

VDD

Monitor

WDT

1

2048 byte

Port 1

I

XRAM

Latch

T

(F005/15 only)

C

C

Port 2

Latch

H

External

Oscillator

o

Circuit

r System Clock

SFR Bus

Internal

e

Oscillator

Port 3

Latch

VREF

DAC0

(12-Bit)

DAC1

(12-Bit)

A

M

Prog

Gain

U

X

TEMP

CP0

ADC

100ksps

CP1

P

P0.0

0

P0.1

P0.2

P0.3

D

P0.4

r

P0.5

v

P0.6

P0.7

P

P1.0

1

P1.1

P1.2

P1.3

D

P1.4

r

P1.5

v

P1.6

P1.7

P

P2.0

2

P2.1

P2.2

P2.3

D

P2.4

r

P2.5

v

P2.6

P2.7

P

P3.0

3

P3.1

P3.2

P3.3

D

P3.4

r

P3.5

v

P3.6

P3.7

9

Rev. 1.7

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