C8051F380 查看數據表（PDF） - Silicon Laboratories
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C8051F380 Datasheet PDF : 321 Pages
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C8051F380/1/2/3/4/5/6/7/C
22.1. Supporting Documents .................................................................................. 206
22.2. SMBus Configuration..................................................................................... 206
22.3. SMBus Operation .......................................................................................... 206
22.3.1. Transmitter Vs. Receiver....................................................................... 207
22.3.2. Arbitration.............................................................................................. 207
22.3.3. Clock Low Extension............................................................................. 207
22.3.4. SCL Low Timeout.................................................................................. 207
22.3.5. SCL High (SMBus Free) Timeout ......................................................... 208
22.4. Using the SMBus........................................................................................... 208
22.4.1. SMBus Configuration Register.............................................................. 208
22.4.2. SMBus Timing Control Register............................................................ 210
22.4.3. SMBnCN Control Register .................................................................... 214
22.4.3.1. Software ACK Generation ............................................................ 214
22.4.3.2. Hardware ACK Generation ........................................................... 214
22.4.4. Hardware Slave Address Recognition .................................................. 217
22.4.5. Data Register ........................................................................................ 221
22.5. SMBus Transfer Modes................................................................................. 223
22.5.1. Write Sequence (Master) ...................................................................... 223
22.5.2. Read Sequence (Master) ...................................................................... 224
22.5.3. Write Sequence (Slave) ........................................................................ 225
22.5.4. Read Sequence (Slave) ........................................................................ 226
22.6. SMBus Status Decoding................................................................................ 226
23. UART0 ................................................................................................................... 232
23.1. Enhanced Baud Rate Generation.................................................................. 233
23.2. Operational Modes ........................................................................................ 234
23.2.1. 8-Bit UART ............................................................................................ 234
23.2.2. 9-Bit UART ............................................................................................ 235
23.3. Multiprocessor Communications ................................................................... 236
24. UART1 ................................................................................................................... 240
24.1. Baud Rate Generator .................................................................................... 241
24.2. Data Format................................................................................................... 242
24.3. Configuration and Operation ......................................................................... 243
24.3.1. Data Transmission ................................................................................ 243
24.3.2. Data Reception ..................................................................................... 243
24.3.3. Multiprocessor Communications ........................................................... 244
25. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 250
25.1. Signal Descriptions........................................................................................ 251
25.1.1. Master Out, Slave In (MOSI)................................................................. 251
25.1.2. Master In, Slave Out (MISO)................................................................. 251
25.1.3. Serial Clock (SCK) ................................................................................ 251
25.1.4. Slave Select (NSS) ............................................................................... 251
25.2. SPI0 Master Mode Operation ........................................................................ 251
25.3. SPI0 Slave Mode Operation .......................................................................... 253
25.4. SPI0 Interrupt Sources .................................................................................. 254
25.5. Serial Clock Phase and Polarity .................................................................... 254
6
Rev. 1.4
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