CA3310AD 查看數據表（PDF） - Intersil

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CA3310AD

CMOS, 10-Bit, A/D Converters with Internal Track and Hold

Intersil 

Timing Diagrams

CLK

tD1 DRDY

DRDY

D0 - D9

INPUT

CA3310, CA3310A

1

2

3

4

5 - 12

13

tD2 DRDY

tHIGH

tD DATA

DATA N - 1

TRACK N

HOLD

1

2

3

tLOW

DATA N

TRACK N + 1

tD APR

FIGURE 1. FREE RUNNING, STRT TIED LOW, DRST TIED HIGH

OEL OR OEM

D0 - D1 OR

D2- D9

OFF TO HIGH

tEN

50%

OFF TO LOW

50%

tDIS

90%

ZL = 50pF TO GND

1kΩ TO GND

TO OUTPUT PIN

10%

ZL = 50pF TO GND

1kΩ TO VDD

FIGURE 2. OUTPUT ENABLE/DISABLE TIMING DIAGRAM

13

1

2

CLK

(INTERNAL)

tR STRT

STRT

DRDY

3

4

5

tD CLK

tW STRT

DON’T CARE

tD3 DRDY

INPUT

HOLD

TRACK

HOLD

FIGURE 3. STRT PULSED LOW, DRST TIED HIGH, INTERNAL CLOCK

6-11

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