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CA5130AE 查看數據表(PDF) - Intersil

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CA5130AE Datasheet PDF : 19 Pages
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CA5130, CA5130A
transistors Q8, Q12 goes essentially to zero. The two preceding
stages in the CA5130, however, continue to draw modest
supply current (see the lower curve in Figure 16) even though
the output stage is strobed off. Figure 1A shows a dual supply
arrangement for the output stage that can also be strobed off,
assuming RL = , by pulling the potential of Terminal 8 down to
that of Terminal 4.
Let it now be assumed that a load resistance of nominal value
(e.g., 2k) is connected between Terminal 6 and ground in
the circuit of Figure 1B. Let it further be assumed that the
input terminal bias (Terminals 2 and 3) is such that the output
terminal (No. 6) voltage is at V+/2. Since PMOS transistor Q8
must now supply quiescent current to both RL and transistor
Q12, it should be apparent that under these conditions the
supply current must increase as an inverse function of the RL
magnitude. Figure 22 shows the voltage drop across PMOS
transistor Q8 as a function of load current at several supply
voltages. Figure 15 shows the voltage transfer characteristics
of the output stage for several values of load resistance.
Wideband Noise
From the standpoint of low noise performance considerations,
the use of the CA5130 is most advantageous in applications
where the source resistance of the input signal is on the order
of 1Mor more. In this case, the total input referred noise
voltage is typically only 23µV when the test circuit amplifier of
Figure 2 is operated at a total supply voltage of 15V. This
value of total input referred noise remains essentially
constant, even though the value of source resistance is raised
by an order of magnitude. This characteristic is due to the fact
that reactance of the input capacitance becomes a significant
factor in shunting the source resistance. It should be noted,
however, that for values of source resistance very much
greater than 1M, the total noise voltage generated can be
dominated by the thermal noise contributions of both the
feedback and source resistors.
Typical Applications
Voltage Followers
Operational amplifiers with very high input resistances, like
the CA5130, are particularly suited to service as voltage
followers. Figure 3 shows the circuit of a classical voltage
follower, together with pertinent waveforms using the
CA5130 in a split supply configuration.
A voltage follower, operated from a single supply, is shown in
Figure 4, together with related waveforms. This follower circuit
is linear over a wide dynamic range, as illustrated by the
reproduction of the output waveform in Figure 4A with input
signal ramping. The waveforms in Figure 4B show that the
follower does not lose its input-to-output phase sense, even
though the input is being swung 7.5V below ground potential.
This unique characteristic is an important attribute in both
operational amplifier and comparator applications. Figure 4B
also shows the manner in which the CMOS output stage
permits the output signal to swing down to the negative supply
rail potential (i.e., ground in the case shown). The digital-to-
analog converter (DAC) circuit, described in the following
section, illustrates the practical use of the CA5130 in a single
supply voltage follower application.
9-Bit CMOS DAC
A typical circuit of a 9-bit Digital-to-Analog Converter (DAC)
(see Note) is shown in Figure 5. This system combines the
concepts of multiple switch CMOS lCs, a low cost ladder
network of discrete metal-oxide film resistors, a CA5130 op
amp connected as a follower, and an inexpensive monolithic
regulator in a simple single power supply arrangement. An
additional feature of the DAC is that it is readily interfaced
with CMOS input logic, e.g., 10V logic levels are used in the
circuit of Figure 5.
NOTE: “Digital-to-Analog Conversion Using the Intersil CD4007A
CMOS lC”, Application Note AN6080.
+7.5V
Rs
3
1M
2
7
+
-
4
8
1
47pF -7.5V
0.01µF
6
0.01
µF
NOISE
VOLTAGE
OUTPUT
30.1k
BW (-3dB) = 200kHz
TOTAL NOISE VOLTAGE (REFERRED
1k
TO INPUT) = 23µV (TYP)
FIGURE 2. CA5130 OUTPUT STAGE IN DUAL AND SINGLE
POWER SUPPLY OPERATION
8

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