CAT25C02VI 查看數據表（PDF） - Catalyst Semiconductor => Onsemi
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CAT25C02VI Datasheet PDF : 15 Pages
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CAT25C01, CAT25C02, CAT25C04
After the correct read instruction and address are sent, Write enable state by pulling the CS low and then
the data stored in the memory at the selected address is clocking the WREN instruction into CAT25C01/02/04.
shifted out on the SO pin. The data stored in the memory The CS must be brought high after the WREN instruction
at the next address can be read sequentially by continuing to enable writes to the device. If the write operation is
to provide clock pulses. The internal address pointer is initiated immediately after the WREN instruction without
automatically incremented to the next higher address CS being brought high, the data will not be written to the
after each byte of data is shifted out. When the highest array because the write enable latch will not have been
address is reached, the address counter rolls over to properly set. Also, for a successful write operation the
0000h allowing the read cycle to be continued indefinitely. address of the memory location(s) to be programmed
The read operation is terminated by pulling the CS high. must be outside the protected address field location
To read the status register, RDSR instruction should
be sent. The contents of the status register are shifted
out on the SO line. The status register may be read at
any time even during a write cycle. Read sequece is
ts illustrated in Figure 4. Reading status register is illustrated
in Figure 5.
r WRITE Sequence
The CAT25C01/02/04 powers up in a Write Disable
a state. Prior to any write instructions, the WREN instruction
must be sent to CAT25C01/02/04. The device goes into
selected by the block protection level.
Byte Write
Once the device is in a Write Enable state, the user may
proceed with a write sequence by setting the CS low,
issuing a write instruction via the SI line, followed by the
8-bit address for CAT25C01/02/04 (for the 25C04, bit 3
of the read data instruction contains address A8).
Programming will start after the CS is brought high.
Figure 6 illustrates byte write sequence.
P Figure 4. Read Instruction Timing
CS
d 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
e SK
u OPCODE
BYTE ADDRESS
SI
0 0 0 0 X0* 0 1 1 A7 A6 A5 A4 A3 A2 A1 A0
tin SO
HIGH IMPEDANCE
n *Please check the instruction set table for address
X=0 for 25010, 25020 ; X=A8 for 25040
o Note: Dashed line = mode (1,1)----
DATA OUT
D7 D6 D5 D4 D3 D2 D1 D0
MSB
c Figure 5. RDSR Instruction Timing
is CS
DSCK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
OPCODE
SI
0
0
0
0
0
1
0
1
SO
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) – – – – –
DATA OUT
7
6
5
4
32
10
MSB
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
Doc. No. 1105, Rev. B
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