CAT25C02SI 查看數據表（PDF） - Catalyst Semiconductor => Onsemi
零件编号
产品描述 (功能)
生产厂家
CAT25C02SI Datasheet PDF : 10 Pages
| |||
CAT25C01/02/04/08/16
Advanced Information
During an internal write cycle, all commands will be
ignored except the RDSR (Read Status Register) in-
struction.
The Status Register can be read to determine if the write
cycle is still in progress. If Bit 0 of the Status Register is
set at 1, write cycle is in progress. If Bit 0 is set at 0, the
device is ready for the next instruction
Page Write
The CAT25C01/02/04/08/16 features page write capa-
bility. After the initial byte, the host may continue to write
up to 16 bytes of data to the CAT25C01/02/04 and 32
bytes of data for 25C08/16. After each byte of data
received, lower order address bits are internally
incremented by one; the high order bits of address will
Figure 6. Write Instruction Timing
remain constant.The only restriction is that the X (X=16
for 25C01/02/04 and X=32 for 25C08/16) bytes must
reside on the same page. If the address counter
reaches the end of the page and clock continues, the
counter will “roll over” to the first address of the page and
overwrite any data that may have been written. The
CAT25C01/02/04/08/16 is automatically returned to the
write disable state at the completion of the write cycle.
Figure 8 illustrates the page write sequence.
To write to the status register, the WRSR instruction
should be sent. Only Bit 2, Bit 3 and Bit 7 of the status
register can be written using the WRSR instruction.
Figure 7 illustrates the sequence of writing to status
register.
CS
012345678
21 22 23 24 25 26 27 28 29 30 31
SK
OPCODE
SI
00 00 00 10
ADDRESS
DATA IN
D7 D6 D5 D4 D3 D2 D1 D0
SO
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) – – – – –
Figure 7. WRSR Timing
CS
SCK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
OPCODE
DATA IN
SI
0
0
0
0
00
0
1
7
6
5
4
32
10
MSB
SO
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) – – – – –
Doc. No. 25067-00 5/00
8
Share Link: 