CAT25C02UI 查看數據表（PDF） - Catalyst Semiconductor => Onsemi
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CAT25C02UI Datasheet PDF : 10 Pages
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Advanced Information
CAT25C01/02/04/08/16
DESIGN CONSIDERATIONS
The CAT25C01/02/04/08/16 powers up in a write
disable state and in a low power standby mode. A
WREN instruction must be issued to perform any writes
to the device after power up. Also,on power up CS
should be brought low to enter a ready state and
receive an instruction. After a successful byte/page
write or status register write, the CAT25C01/02/04/08/
16 goes into a write disable mode. CS must be set high
after the proper number of clock cycles to start an
internal write cycle. Access to the array during an
internal write cycle is ignored and programming is
continued. On power up, SO is in a high impedance. If
an invalid op code is received, no data will be shifted
into the CAT25C01/02/04/08/16, and the serial output
pin (SO) will remain in a high impedance state until the
falling edge of CS is detected again.
Figure 8. Page Write Instruction Timing
CS
012345678
21 22 23 24-31 32-39 24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1
SK
OPCODE
SI
00 00 00 10
ADDRESS
DATA IN
Data Data Data
Byte 1 Byte 2 Byte 3
Data Byte N
7..1
0
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) – – – – –
Figure 9. HOLD Timing
CS
tCD
tCD
SCK
tHD
HOLD
tHD
tHZ
SO
Note: Dashed Line= mode (1, 1) – – – – –
Figure 10. WP Timing
HIGH IMPEDANCE
tLZ
tWPS
tWPH
CS
SCK
tCSH
WP
WP
Note: Dashed Line= mode (1, 1) – – – – –
9
Doc. No. 25067-00 5/00
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