CAT28LV64G-15T 查看數據表（PDF） - Catalyst Semiconductor => Onsemi
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CAT28LV64G-15T Datasheet PDF : 12 Pages
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Figure 1. A.C. Testing Input/Output Waveform(4)
VCC - 0.3 V
0.0 V
INPUT PULSE LEVELS
2.0 V
0.6 V
REFERENCE POINTS
Figure 2. A.C. Testing Load Circuit (example)
Vcc
DEVICE
UNDER
TEST
1. 3K
1.8 K
OUTPUT
CL= 100 pF
CAT28LV64
CL INCLUDES JIG CAPACITANCE
A.C. CHARACTERISTICS, Write Cycle
Vcc = 3.0V to 3.6V, unless otherwise specified.
Symbol
tWC
tAS
tAH
tCS
tCH
tCW(2)
tOES
tOEH
tWP(2)
tDS
tDH
tINIT(1)
tBLC(1)(3)
Parameter
Write Cycle Time
Address Setup Time0
Address Hold Time
CE Setup Time
CE Hold Time
CE Pulse Time
OE Setup Time
OE Hold Time
WE Pulse Width
Data Setup Time
Data Hold Time
Write Inhibit Period
After Power-up
Byte Load Cycle Time
28LV64-15
Min
Max
5
0
100
0
0
110
0
0
110
60
0
5
10
0.05
100
28LV64-20
Min
Max
5
0
100
0
0
150
10
10
150
100
0
28LV64-25
Min Max
5
0
100
0
0
150
10
10
150
100
0
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
10
5
10
ms
0.1
100 0.1 100
µs
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) A write pulse of less than 20ns duration will not initiate a write cycle.
(3) A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
however a transition from HIGH to LOW within tBLC max. stops the timer.
(4) Input rise and fall times (10% and 90%) < 10 ns.
5
Doc. No. 1010, Rev. D
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