CAT5132 查看數據表（PDF） - ON Semiconductor
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CAT5132 Datasheet PDF : 12 Pages
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CAT5132
Table 7. A.C. CHARACTERISTICS
Symbol
Parameter (see Figure 6)
FSCL
Clock Frequency
TI (Note 11) Noise Suppression Time Constant at SCL & SDA Inputs
tAA
SLC Low to SDA Data Out and ACK Out
tBUF (Note 11) Time the bus must be free before a new transmission can start
tHD:STA
Start Condition Hold Time
tLOW
Clock Low Period
tHIGH
Clock High Period
tSU:STA
Start Condition Setup Time (for a Repeated Start Condition)
tHD:DAT
Data in Hold Time
tR (Note 11) SDA and SCL Rise Time
tF (Note 11) SDA and SCL Fall Time
tSU:STO
Stop Conditions Setup Time
tDH
Data Out Hold Time
11. This parameter is tested initially and after a design or process change that affects the parameter.
Table 8. POWER UP TIMING (Notes 12, 13)
Symbol
tPUR
tPUW
Power-up to Read Operation
Power-up to Write Operation
Parameter
VCC = 2.7 − 5.5 V
Min
Max
400
50
1
1.2
0.6
1.2
0.6
0.6
0
0.3
300
0.6
100
Min
Max
1
1
Units
kHz
ns
ms
ms
ms
ms
ms
ms
ns
ms
ns
ms
ns
Units
ms
ms
Table 9. WIPER TIMING
Symbol
Parameter
tWRPO
tWRL
Wiper Response Time After Power Supply Stable
Wiper Response Time After Instruction Issued
Min
Max
Units
5
10
ms
5
10
ms
Table 10. WRITE CYCLE LIMITS
Symbol
Parameter
Min
Max
Units
tWR
Write Cycle Time (see Figure 7)
5
ms
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
Table 11. RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
Max
NEND (Note 12) Endurance
MIL−STD−883, Test Method 1033
100,000
TDR (Note 12)
Data Retention
MIL−STD−883, Test Method 1008
100
12. This parameter is tested initially and after a design or process change that affects the parameter.
13. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Units
Cycles
Years
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