CAT706V 查看數據表（PDF） - ON Semiconductor

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CAT706V

µP Supervisory Circuits

ON Semiconductor 

CAT705, CAT706, CAT813

FUNCTIONAL DESCRIPTION

PROCESSOR RESET

The CAT705, CAT706 & CAT813 detect supply

voltage (VCC) conditions that are below the specified

voltage trip value (VRST) and provide a reset output to

maintain correct system operation. On power-up,

R¯¯E¯S¯E¯T¯ (or RESET for the CAT813) are kept active for

a minimum delay tRP of 140ms after the supply voltage

(VCC) rises above VRST to allow the power supply and

processor to stabilize. When VCC drops below the

voltage trip value (VRST), the reset output signals

R¯¯E¯S¯E¯T¯ (or RESET) are pulled active. R¯¯E¯S¯E¯T¯ (or

RESET) is specifically designed to provide the reset

input signals for processors. This provides reliable

and consistent operation as power is turned on, off or

during brownout conditions by maintaining the

processor operation in known conditions.

MANUAL RESET

The CAT705, CAT706 & CAT813 each have a Manual

Reset (¯M¯R¯) input to allow for alternative control of the

reset outputs. The ¯M¯R¯ input is designed for direct

connection to a pushbutton (see Figure 1). The ¯M¯R¯

input is internally pulled up by 52kΩ resistor and must

be pulled low to cause the reset output to go active.

Internally, this input is debounced and timed such that

R¯¯E¯S¯E¯T¯ (or RESET) signals of at least 140ms

minimum will be generated. The min 140ms tRP delay

commences as the Manual Reset input is released

from the low level. (see Figure 2)

MR

RESET

RESET

MR

WDO

VCC

GND

PFI

CAT705

CAT706

CAT813

RESET/RESET

WDI

PFO

Figure 1. Pushbutton RESET

tPB

tPDLY

VIL

VIH

tRP

VOH

VOL

Figure 2. Timing Diagram – Pushbutton RESET

© 2010 SCILLC. All rights reserved.

7

Characteristics subject to change without notice

Doc. No. MD-3030, Rev. D

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