CD4094 查看數據表（PDF） - Intersil
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CD4094 Datasheet PDF : 11 Pages
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CD4094BMS
SERIAL
IN
*
2
DQ
CL
1
CL
DQ
CL
2
CL
CLOCK
*
3
STROBE
*
1
OUTPUT
ENABLE
*
15
TR
CL
CL
pn
TR
TR
p
n
TR
TR
TR
LATCH
1
TR
LATCH
TR
2
STAGES
3-7
CL
p
DQn
CL
8
CL
Q
CL
CL
p
n
CL
TR
LATCH
TR
8
SERIAL
OUT
10
Q’S
SERIAL
OUT
9
QS
* VDD
3-STATE
1
p
n
3-
STATE
2
VDD
VSS
4
5
6 7 14 13 12
Q1
Q2
Q3 Q4 Q5 Q6 Q7
3-
STATE
8
VSS
* ALL INPUTS
PROTECTED BY
CMOS PROTECTION
NETWORK
11
Q8
FIGURE 1. LOGIC DIAGRAM
TRUTH TABLE
OUTPUT
PARALLEL OUTPUTS SERIAL OUTPUTS
CL∆
ENABLE STROBE DATA
Q1
QN
QS*
Q’S
0
X
X
OC
OC
Q7
NC
0
X
X
OC
OC
NC
Q7
1
0
X
NC
NC
Q7
NC
1
1
0
0
QN-1
Q7
NC
1
1
1
1
QN-1
Q7
NC
1
1
1
NC
NC
NC
Q7
∆ = Level Change
X = Don’t Care
Logic 1 = High
Logic 0 = Low
NC = No Change
OC = Open Circuit
* At the positive clock edge information in the 7th shift register stage is transferred to the 8th register stage
and the QS output
7-1089
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