CD4517 查看數據表（PDF） - Intersil
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CD4517 Datasheet PDF : 9 Pages
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Specifications CD4517BMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS (Continued)
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
Irradiation
1, 2, 5, 6, 10, 11,
8
3, 4, 7, 9, 12, 13,
(Note 2)
14, 15
16
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V
Logic Diagram
*
CL
*
D
CL
CL
1
DQ
CL
CL
2
DQ
CL
CL
15
DQ
CL
CL
16
DQ
WE
WE
p
p
n
n
WE
WE
VDD
CL
CL
Q16* 17
DQ
CL
CL
31
DQ
WE
*
WE
WE
WE
WE
VSS
CL
CL
VDD
VDD
CL
CL
33
D 32
DQ
SAME AS
STAGES
Q32*
WE
16
WE
Q
VSS
VSS
* All inputs protected by CMOS protection network.
Q32*
CL
CL
CL
CL
CL
47
CL
49
DQ
D 48
DQ
SAME AS
STAGES Q48*
WE 16 & 32
WE
Q
Q48*
CL
CL
CL
CL
63
DQ
D 64
SAME AS
STAGES
WE
16, 32, 48
EXCEPT
WE FOR Q*Q
Q64*
FIGURE 1. LOGIC BLOCK DIAGRAM
TRUTH TABLE
CLOCK WRITE ENABLE DATA STAGE 16 TAP STAGE 32 TAP STAGE 48 TAP STAGE 64 TAP
0
0
X
Q16
Q32
Q48
Q64
0
1
X
Z
Z
Z
Z
1
0
X
Q16
Q32
Q48
Q64
1
1
X
Z
Z
Z
Z
0
DI In
Q16
Q32
Q48
Q64
1
DI In
D17 In
D33 In
D49 In
Z
0
X
Q16
Q32
Q48
Q64
1
X
Z
Z
Z
Z
1 = HIGH LEVEL
0 = LOW LEVEL
X = DON’T CARE
Z = HIGH IMPEDANCE
7-1202
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