CD74HCT670M 查看數據表（PDF） - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS

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CD74HCT670M

High-Speed CMOS Logic 4x4 Register File

TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS 

CD54HC670, CD74HC670, CD74HCT670

Functional Diagram

15

D0 1

D1 2

D2 3

D3 12

WE 11

RE

RA1

RA0

WA0

WA1

4 5 14 13

10 Q0

9 Q1

7

Q2

6

Q3

WRITE MODE SELECT TABLE

OPERATING

MODE

Write Data

INPUTS

WE

DN

L

L

INTERNAL

LATCHES

(NOTE 1)

L

L

H

H

Data Latched

H

X

No Change

NOTE:

1. The Write Address (WA0 and WA1) to the “internal latches” must

be stable while WE is LOW for conventional operation.

READ MODE SELECT TABLE

INPUTS

OPERATING

MODE

RE

Read

L

INTERNAL

LATCHES

(NOTE 2)

L

OUTPUT

QN

L

L

H

H

Disabled

H

X

(Z)

NOTE:

2. The selection of the “internal latches” by Read Address (RA0 and

RA1) are not constrained by WE or RE operation.

H = High Voltage Level

L = Low Voltage Level

X= Don’t Care

Z = High Impedance “Off” State

2

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