CDP1802AC/3 查看數據表（PDF） - Intersil

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CDP1802AC/3

High-Reliability CMOS 8-Bit Microprocessor

Intersil 

CDP1802AC/3

Machine Cycle Timing Waveforms (Propagation Delays Not Shown) (Continued)

INSTRUCTION

MRD

FETCH (S0)

MEMORY READ CYCLE

EXECUTE (S1)

MEMORY READ CYCLE

FETCH (S0)

MEMORY READ CYCLE

EXECUTE

MWR (HIGH)

MEMORY

OUTPUT

ALLOWABLE MEMORY ACCESS

VALID OUTPUT

“DON’T CARE” OR INTERNAL DELAYS

VALID

OUTPUT

HIGH IMPEDANCE STATE

FIGURE 6. MEMORY READ CYCLE TIMING WAVEFORMS

VALID

OUTPUT

INSTRUCTION

MRD

FETCH (S0)

MEMORY READ CYCLE

EXECUTE (S1)

MEMORY READ CYCLE

EXECUTE (S1)

MEMORY READ CYCLE

FETCH (S0)

MWR (HIGH)

MEMORY

OUTPUT

ALLOWABLE MEMORY ACCESS

VALID OUTPUT

“DON’T CARE” OR INTERNAL DELAYS

VALID OUTPUT

HIGH IMPEDANCE STATE

FIGURE 7. LONG BRANCH OR LONG SKIP CYCLE TIMING WAVEFORMS

VALID

OUTPUT

FN1441 Rev 3.00

October 17, 2008

Page 10 of 27

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