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CDP1802A 查看數據表(PDF) - Intersil

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CDP1802A
Intersil
Intersil Intersil
CDP1802A Datasheet PDF : 28 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
CDP1802A, CDP1802AC, CDP1802BC
Dynamic Electrical Specifications TA = -40oC to +85oC, CL = 50pF, VDD ±5%, Except as Noted (Continued)
TEST
CONDITIONS
CDP1802A,
CDP1802AC
CDP1802BC
PARAMETER
EF1-4 Set Up
(NOTE 1)
SYMBOL VCC (V) VDD (V)
TYP
tSU
5
5
-30
5
10
-20
MAX
20
30
(NOTE 1)
TYP
-30
-
MAX
0
-
10
10
-10
40
-
-
EF1-4 Hold
tH
5
5
150
200
100
150
(Note 2)
5
10
100
150
-
-
10
10
75
100
-
-
Minimum Pulse Width Times
CLEAR Pulse Width
tWL
5
5
150
300
100
150
(Note 2)
5
10
100
200
-
-
10
10
75
150
-
-
CLOCK Pulse Width
tWL
5
5
125
150
90
100
5
10
100
125
-
-
10
10
60
75
-
-
NOTES:
1. Typical values are for TA = +25oC and nominal VDD.
2. Maximum limits of minimum characteristics are the values above which all devices function.
Timing Specifications as a function of T(T = 1/fCLOCK) at TA = -40 to +85oC, Except as Noted
TEST CONDITIONS
CDP1802A,
CDP1802AC
CDP1802BC
PARAMETERS
High-Order Memory-Address Byte
Set Up to TPA
Time
SYMBOL
tSU
VCC (V)
5
5
VDD (V)
5
10
MIN
2T-550
2T-350
(NOTE 1)
TYP
2T-400
2T250
MIN
2T-325
-
(NOTE 1)
TYP
2T-275
-
10
10
2T-250 2T-200
-
-
High-Order Memory-Address Byte
tH
5
5
t/2-25
T/2-15
T/2-25
T/2-15
Hold After TPA Time
5
10
T/2-35
T/2-25
-
-
10
10
T/2-10
T/2-+0
-
-
Low-Order Memory-Address Byte
tH
5
5
T-30
T+0
T-30
T+0
Hold After WR Time
5
10
T-20
T+0
-
-
10
10
T-10
T+0
-
-
CPU Data to Bus Hold After WR
tH
5
5
T-200
T-150
T-175
T-125
Time
5
10
T-150
T-100
-
-
10
10
T-100
T-50
-
-
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3-10

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