CDP1822C/3 查看數據表（PDF） - Intersil
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CDP1822C/3 Datasheet PDF : 5 Pages
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CDP1822C/3
Read Cycle Dynamic Electrical Specifications tR, tF = 10ns, CL = 50pF
PARAMETER
SYMBOL
VDD
(V)
LIMITS
+25oC, -55oC
+125oC
MIN
MAX
MIN
MAX
UNITS
Read Cycle (Note 1)
tRC
5
370
-
500
-
ns
Access from Address (Note 1)
tADA
5
-
370
-
500
ns
Output Valid from Chip Select 1 (Note 1)
tDOA1
5
-
370
-
500
ns
Output Valid from Chip Select 2 (Note 1)
tDOA2
5
-
370
-
500
ns
Output Active from Output Disable (Note 1)
tDOA3
5
-
170
-
225
ns
Output Hold from Chip Select 1
tDOH1
5
10
-
20
-
ns
Output Hold from Chip Select 2
tDOH2
5
10
-
20
-
ns
Output Hold from Output Disable
tDOH3
5
10
-
20
-
ns
NOTE:
1. Limits designate 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing
A0 - A7
CHIP
SELECT 1
CHIP
SELECT 2
OUTPUT
DISABLE
tRC
tADA
tDOA1
(NOTE 1)
tDOA2
(NOTE 1)
tDOA3
(NOTE 1)
tDOH1
tDOH2
tDOH3
VDD
VSS
WRITE
ADDRESS
DECODER
READ
ADDRESS
DECODER
READ/
WRITE
DATA OUT
HIGH
IMPEDANCE
DATA OUT
VALID
HIGH
IMPEDANCE
NOTE: Minimum timing for valid data output. Longer times will initiate an
earlier but invalid output.
FIGURE 1. READ CYCLE WAVEFORMS AND TIMING DIAGRAM
VDD
FIGURE 2. MEMORY CELL CONFIGURATION
6-21
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