CE2746 查看數據表（PDF） - Unspecified

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CE2746

6-Channel Audio DAC, 24-bit, 192kHz

Unspecified 

CE2746

AUTODET Automatically detects the serial audio input data sampling rate

0: - do not use auto-detect

1: - automatically detects the serial audio input data sampling rate.

FS384: 384 fs or 256 fs control for the PLL clock output

0: the PLL takes the reference clock and multiplies it by 2 to generate a 512 bit clock

1: the PLL takes the reference clock and multiplies it by 4/3 to generate a 512 bit clock

CKDIV4: Clock divider enable control

0: do not enable input clock divided by 4

1: enable input clock divided by 4

CKDIV2: Clock divider enable control

0: do not enable input clock divided by 2

1: enable input clock divided by 2

MUTE56: Mute control for channels 5 and 6

0: do not mute channels 5 and 6

1: simultaneously mute channels 5 and 6

MUTE34: Mute control for channels 3 and 4

0: do not mute channels 3 and 4

1: simultaneously mute channels 3 and 4

MUTE12: Mute control for channels 1 and 2

0: do not mute channels 1 and 2

1: simultaneously mute channels1 and2

Volume Registers for channel 1 to channel 3, (ADRS=hex02 - hex07, default=hex80)

ADDR[3:0]

Hex 02

Hex 03

Hex 04

Hex 05

Hex 06

Hex 07

Default Value

Volume Registers

BIT 7

BIT 6

BIT 5

BIT 4

Channel 1 left volume register, VOLREGL1[7:0]

Channel 1 right volume register, VOLREGR1[7:0]

Channel 2 left volume register, VOLREGL2[7:0]

Channel 2 right volume register, VOLREGR2[7:0]

Channel 3 left volume register, VOLREGL3[7:0]

Channel 3 right volume register, VOLREGR3[7:0]

1

0

0

0

BIT 3

0

BIT 2

0

BIT 1

0

VOLREG:- Control the volume of the 6 DAC’s

80h- corresponds to 0 dB setting. Value should not be programed greater than 80h.

BIT 0

0

11-18

March 24, 2004

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