CE2746 查看數據表（PDF） - Unspecified
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CE2746 Datasheet PDF : 18 Pages
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Figure 1. Audio Serial Input Data Timing Diagram
CE2746
LRCK
LEFT CHANNEL
1/fs
RIGHT CHANNEL
BCK
DIN1,2,3
MSB
LSB
MSB
210
Right justified, CREG0[7,6]=[0 0]
LSB
210
LRCK
BCK
MSB
DIN1,2,3
LEFT CHANNEL
LSB
0
1/fs
RIGHT CHANNEL
MSB
LSB
10
LRCK
BCK
DIN1,2,3
Left justified, CREG0[7,6]=[1 0]
LEFT CHANNEL
1/fs
RIGHT CHANNEL
MSB
LSB
MSB
10
I2S, CREG0[7,6]=[0 1]
LSB
10
7-18
March 24, 2004
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