CHA2092B 查看數據表（PDF） - United Monolithic Semiconductors
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CHA2092B Datasheet PDF : 6 Pages
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CHA2092b
Typical Bias Tuning
The circuit schematic is given below :
IN
18-32GHz Low Noise Amplifier
Vd 1,2,3
O UT
Vg 1
Vg 2,3
The three drain biases are connected altogether on chip. For typical operation, all the gate
biases are connected together at the same power supply, tuned to drive a small signal
operating current of 60 mA. A separate access to the gate voltages of the first stage ( Vg1 )
and the second and third stages ( Vgs2,3 ) is provided for the fine tuning of the amplifier
regarding the application.
Ordering Information
Chip form :
CHA2092b99F/00
Information furnished is believed to be accurate and reliable. However United Monolithic Semiconductors
S.A.S. assumes no responsability for the consequences of use of such information nor for any infringement of
patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of United Monolithic Semiconductors S.A.S.. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all
information previously supplied. United Monolithic Semiconductors S.A.S. products are not authorised for use
as critical components in life support devices or systems without express written approval from United
Monolithic Semiconductors S.A.S.
Ref. : DSCHA20921233 21-August-01
6/6
Specifications subject to change without notice
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