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CM1236 查看數據表(PDF) - ON Semiconductor

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CM1236 Datasheet PDF : 14 Pages
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CM1236
CM1236 Application and Guidelines
As a general rule, the CM1236 ESD protection array should be located as close as possible to the point of entry
of expected electrostatic discharges with minimum PCB trace lengths to the ground planes and between the sig-
nal input and the ESD device to minimize stray series inductance.
Figure 8. Application of Positive ESD Pulse Between Input Channel and Ground
Figure 9. Typical PCB Layout
Additional Information
See also California Micro Devices Application Note AP209, “Design Considerations for ESD Protection,” in the
Applications section at www.calmicro.com.
Rev. 3 | Page 11 of 14 | www.onsemi.com

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