GS8170DW18C-250I 查看數據表（PDF） - Giga Semiconductor

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GS8170DW18C-250I

18Mb Σ1x1 Double Late Write SigmaRAM™ SRAM

Giga Semiconductor 

CK

Address

ADV

/E1

/E2 Bank 1

E2 Bank 2

DQ

Bank 1

CQ

Bank 1

Preliminary

GS8170DW18/36/72C-333/300/250

Echo Clock Control in Two Banks of SigmaRAM Pipelined SRAMs

Read

Read

Read

Read

Read

A

B

C

D

E

F

QA

QC

CQ1 + CQ2

CQ

Bank 2

DQ

Bank 2

QB

QD

Note: E1\ does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously deselected by E2 or E3 being sampled false.

It should be noted that deselection of the RAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of

Echo Clock drivers is always pipelined to the same degree as output data. Deselection of the RAM via E1 does not deactivate the

Echo Clocks.

In some applications it may be appropriate to pause between banks (i.e., to deselect both RAMs with E1 before resuming read

operations). An E1 deselect at a bank switch will allow at least one clock to be issued from the new bank before the first read cycle

in the bank. Although the following drawing illustrates a E1 read pause upon switching from Bank 1 to Bank 2, a write to Bank 2

would have the same effect, causing the RAM in Bank 2 to issue at least one clock before it is needed.

Rev: 1.00d 6/2002

16/36

© 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

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