GS8180D18D-333 查看數據表（PDF） - Giga Semiconductor
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GS8180D18D-333 Datasheet PDF : 27 Pages
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Preliminary
GS8180D18D-333/300/250/200
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaQuad SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to VSS via an external
resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the intended line
impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a vendor-specified tolerance is between
150Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may
move the output driver impedance level one step at a time towards the optimum level. The output driver is implemented with discrete binary
weighted impedance steps. Impedance updates for “0s” occur whenever the SRAM is driving “1s” for the same DQs (and vice-versa for “1s”) or
the SRAM is in HI-Z. The SRAM requires 32K start-up cycles, selected or deselected, after VDD reaches its operating range to reach its
programmed output driver impedance.
Separate I/O Σ2x2B4 SigmaQuad SRAM Truth Table
A
R
W
Previous
Operation
Current
Operation
D
D
D
D
Q
Q
Q
Q
K↑ K↑ K↑
K↑
(tn) (tn) (tn)
(tn-1)
K↑
K↑ K↑ K↑ K↑ K↑ K↑ K↑ K↑
(tn)
(tn+1) (tn+1½) (tn+2) (tn+2½) (tn+1) (tn+1½) (tn+2) (tn+2½)
X11
Deselect
Deselect
X
X
—
—
Hi-Z Hi-Z
—
—
X1X
Write
Deselect
D2
D3
—
—
Hi-Z Hi-Z
—
—
XX1
Read
Deselect
X
X
—
—
Q2
Q3
—
—
V10
Deselect
Write
D0
D1
D2
D3
Hi-Z Hi-Z
—
—
V0X
Deselect
Read
X
X
—
—
Q0
Q1
Q2
Q3
VX0
Read
Write
D0
D1
D2
D3
Q2
Q3
—
—
V0X
Write
Read
D2
D3
—
—
Q0
Q1
Q2
Q3
Notes:
1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”
2. “—” indicates that the input requirement or output state is determined by the next operation.
3. Q0, Q1, Q2, and Q3 indicate the first, second, third, and fourth pieces of output data transferred during Read operations.
4. D0, D1, D2, and D3 indicate the first, second, third, and fourth pieces of input data transferred during Write operations.
5. Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except
when preceded by a Read command.
6. CQs are never tristated.
7. Users should not clock in metastable addresses.
Rev: 2.00f 6/2002
10/27
© 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
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