GS8180D18D-333I 查看數據表（PDF） - Giga Semiconductor

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GS8180D18D-333I

18Mb Σ2x2B4 SigmaQuad SRAM

Giga Semiconductor 

Preliminary

GS8180D18D-333/300/250/200

Background

Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are needed.

Therefore, the SigmaQuad SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O SRAMs are unpopular in

applications where multiple reads or multiple writes are needed because burst read or write transfers from Separate I/O SRAMs can cut the

RAM’s bandwidth in half.

A SigmaQuad SRAM can begin an alternating sequence of reads and writes with either a read or a write. In order for any separate I/O SRAM that

shares a common address between its two ports to keep both ports running all the time, the RAM must implement some sort of burst transfer

protocol. The burst must be at least long enough to cover the time the opposite port is receiving instructions on what to do next. The rate at which

a RAM can accept a new random address is the most fundamental performance metric for the RAM. Each of the three SigmaQuad SRAMs

support similar address rates because random address rate is determined by the internal performance of the RAM and they are all based on the

same internal circuits. Differences between the truth tables of the different SigmaQuad SRAMs, or any other Separate I/O SRAMs, follow from

differences in how the RAM’s interface is contrived to interact with the rest of the system. Each mode of operation has its own advantages and

disadvantages. The user should consider the nature of the work to be done by the RAM to evaluate which version is best suited to the application

at hand.

Alternating Read-Write Operations

SigmaQuad SRAMs follow a few simple rules of operation.

- Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port.

- Read or Write data transfers in progress may not be interrupted and re-started.

- R and W high always deselects the RAM but does not disable the CQ or CQ output pins.

- All address, data, and control inputs are sampled on clock edges.

In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for details.

Rev: 2.00f 6/2002

4/27

© 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

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