GS8180D18D-300 查看數據表（PDF） - Giga Semiconductor
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GS8180D18D-300 Datasheet PDF : 27 Pages
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Preliminary
GS8180D18D-333/300/250/200
Σ2x2B4 SigmaQuad SRAM DDR Write
The status of the Address Input, W, and R pins are sampled at each rising edge of K. W and R high causes chip disable. A low on the Write
Enable-bar pin, W, and a high on the Read Enable-bar pin, R, begins a write cycle. W is always ignored if the previous command was a write
command. Data is clocked in by the next rising edge of K, the rising edge of K after that, the next rising edge of K, and finally by the next rising
edge of K.
Σ2x2B4 Double Data Rate SigmaQuad SRAM Write First
Dwg Rev. G
No Op
W ri te
Read
W ri te
Read
W ri te
K
/K
Address
XX
B
C
D
E
F
/R
/W
/BWx
D
DB0
DB1
DB2
DB3
DD0
DD1
DD2
C
/C
QC0
QC1
QC2
Q
CQ
/CQ
Special Functions
Byte Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with a particular
byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address
at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low during the data in sample times in a write
sequence.
Rev: 2.00f 6/2002
6/27
© 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
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