WME128K8-150CI 查看數據表（PDF） - White Electronic Designs Corporation
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WME128K8-150CI Datasheet PDF : 11 Pages
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White Electronic Designs
WME128K8-XXX
READ
Figure 3 shows Read cycle waveforms. A read cycle begins
with selection address, chip select and output enable. Chip
select is accomplished by placing the CS# line low. Output
enable is done by placing the OE# line low. The memory
places the selected data byte on I/O0 through I/O7 after
the access time. The output of the memory is placed in a
high impedance state shortly after either the OE# line or
CS# line is returned to a high level.
FIGURE 3 – READ WAVEFORMS
ADDRESS
t RC
ADDRESS VALID
CS#
OE#
t ACS
t OE
OUTPUT
t ACC
HIGH Z
NOTE:
OE# may be delayed up to tACS- tOE after the falling edge of CS#
without impact on tOE or by tACC- tOE after an address change without impact on tACC.
t DF
t OH
OUTPUT
VALID
AC READ CHARACTERISTICS (See Figure 3)
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Read Cycle Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Hold from Address Change, OE# or CS#
Output Enable to Output Valid
Chip Select or OE# to High Z Output
Symbol
tRC
tACC
tACS
tOH
tOE
tDF
-120
Min Max
120
120
120
0
0 50
60
-140
Min Max
140
140
140
0
0 55
70
-150
Min Max
150
150
150
0
0 55
70
-200
Min Max
200
200
200
0
0 55
70
-250
Min Max
250
250
250
0
0 85
70
-300
Unit
Min Max
300
ns
300 ns
300 ns
0
ns
0 85 ns
70 ns
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2004
Rev. 5
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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