WME128K8-120CQ 查看數據表（PDF） - White Electronic Designs Corporation
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WME128K8-120CQ Datasheet PDF : 11 Pages
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White Electronic Designs
WME128K8-XXX
WRITE
Write operations are initiated when both CS# and WE#
are low and OE# is high. The EEPROM devices support
both a CS# and WE# controlled write cycle. The address is
latched by the falling edge of either CS# or WE#, whichever
occurs last.
The data is latched internally by the rising edge of either
CS# or WE#, whichever occurs first. A byte write operation
will automatically continue to completion.
WRITE CYCLE TIMING
Figures 4 and 5 show the write cycle timing relationships.
A write cycle begins with address application, write enable
and chip select. Chip select is accomplished by placing
the CS# line low. Write enable consists of setting the WE#
line low. The write cycle begins when the last of either CS#
or WE# goes low.
The WE# line transition from high to low also initiates
an internal 150µsec delay timer to permit page mode
operation. Each subsequent WE# transition from high to
low that occurs before the completion of the 150µsec time
out will restart the timer from zero. The operation of the
timer is the same as a retriggerable one-shot.
AC WRITE CHARACTERISTICS
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Write Cycle Time, TYP = 6ms
Address Set-up Time
Write Pulse Width (WE# or CS#)
Chip Select Set-up Time
Address Hold Time
Data Hold Time
Chip Select Hold Time
Data Set-up Time
Output Enable Set-up Time
Output Enable Hold Time
Write Pulse Width High
128Kx8
Symbol
Unit
Min
Max
tWC
10
ms
tAS
10
ns
tWP
100
ns
tCS
0
ns
tAH
100
ns
tDH
10
ns
tCH
0
ns
tDS
50
ns
tOES
0
ns
tOEH
0
ns
tWPH
50
ns
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2004
Rev. 5
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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