COM20020 查看數據表（PDF） - SMSC -> Microchip

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COM20020

COM20020 3.3V ULANC Universal Local Area Network Controller with 2K x 8 On-Board RAM

SMSC -> Microchip 

High Speed CPU Bus Timing Support

High speed CPU bus support was added to the

COM20020. The reasoning behind this is as

follows: With the Host interface in Non-

multiplexed Bus mode, I/O address and Chip

Select signals must be stable before the read

signal is active and remain after the read signal

is inactive. But the High Speed CPU bus timing

doesn't adhere to these timings. For example, a

RISC type single chip microcontroller (like the

HITACHI SuperH series) changes I/O address at

the same time as the read signal. Therefore,

several external logic ICs would be required to

connect to this microcontroller.

In addition, the Diagnostic Status (DIAG) register

is cleared automatically by reading itself. The

internal DIAG register read signal is generated

by decoding the Address (A2-A0), Chip Select

(nCS) and Read (nRD) signals. The decoder will

A2-A0, nCS

generate a noise spike at the above tight timing.

The DIAG register is cleared by the spike signal

without reading itself. This is unexpected

operation. Reading the internal RAM and Next

Id Register have the same mechanism as

reading the DIAG register.

Therefore, the address decode and host

interface mode blocks were modified to fit the

above CPU interface to support high speed CPU

bus timing. In Intel CPU mode (nRD, nWR

mode), 3 bit I/O address (A2-A0) and Chip Select

(nCS) are sampled internally by Flip-Flops on the

falling edge of the internal delayed nRD signal.

The internal real read signal is the more delayed

nRD signal. But the rising edge of nRD doesn't

delay. By this modification, the internal real

address and Chip Select are stable while the

internal real read signal is active. Refer to figure

4 below.

VALID

nRD

Delayed nRD

(nRD1)

Sampled A2-A0, nCS

More delayed nRD

(nRD2)

VALID

FIGURE 4 - HIGH SPEED CPU BUS TIMING - INTEL CPU MODE

The I/O address and Chip Select signals, which Diagnostic register and generates the starting

are supplied to the data output logic, are not pulse of the RAM Arbitration. Typical delay time

sampled. Also, the nRD signal is not delayed, between nRD and nRD1 is around 15nS and

because the above sampling and delaying paths between nRD1 and nRD2 is around 10nS.

decrease the data access time of the read cycle.

Longer pulse widths are needed due to these

The above sampling and delaying signals are delays on nRD signal. However, the CPU can

supplied to the Read Pulse Generation logic insert some wait cycles to extend the width

which generates the clearing pulse for the without any impact on performance.

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