CPC7581BB 查看數據表（PDF） - IXYS CORPORATION
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CPC7581BB Datasheet PDF : 15 Pages
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INTEGRATED CIRCUITS DIVISION
CPC7581
2.2.1 Make-Before-Break Operation Logic Table (Ringing to Talk Transition)
State INRINGING Latch
Ringing
1
Make-
Before-
0
0
Break
Talk
0
TSD
Timing
Break
Switches
-
Off
SW4 waiting for next zero-current crossing to
turn off. Maximum time is one-half of the ringing
Z cycle. In this transition state, current that is
On
limited to the dc break switch current limit value
will be sourced from the ring node of the SLIC.
Zero-cross current has occurred
On
Ringing
Return
Switch
(SW3)
On
Off
Off
Ringing
Switch
(SW4)
On
On
Off
To use break-before-make ringing switch release
timing, assert TSD during ringing. This causes the
operational sequence shown in “Break-Before-Make
Operation Logic Table (Ringing to Talk Transition)” on
page 11 to occur. Logic states and explanations are
given in “Truth Table” on page 9.
2.2.2 Break-Before-Make Operation Logic Table (Ringing to Talk Transition)
State INRINGING Latch
Ringing
1
All-off
1
0
All-off
1
Talk
0
TSD
Timing
Z
-
Hold this state for one-half of the ringing cycle.
0 SW4 waiting for zero current to turn off.
Zero current has occurred. SW4 has opened
Z
Release break switches
Break
Switches
Off
Off
Off
On
Ringing
Return
Switch
(SW3)
On
Off
Off
Off
Ringing
Switch
(SW4)
On
On
Off
Off
2.3 Data Latch
The CPC7581 has an integrated data latch. The latch
operation is controlled by logic-level input pin 11
(LATCH). The data input of the latch is pin 10
(INRINGING), while the output of the data latch is an
internal node used for state control. When the LATCH
control pin is at logic 0, the data latch is transparent
and data control signals flow directly through to state
control. A change in input will be reflected in a change
is switch state. When the LATCH control pin is at logic
1, the data latch is active and a change in input control
will not affect switch state. The switches will remain in
the position they were in when the LATCH changed
from logic 0 to logic 1 and will not respond to changes
in input as long as the latch is at logic 1. The TSD input
is not tied to the data latch. Therefore, TSD is not
affected by the LATCH input and the TSD input will
override state control.
2.4 TSD
The thermal shutdown mechanism activates when the
device die temperature reaches a minimum of 110° C,
placing the device in the all-off state regardless of
logic input. During thermal shutdown mode, pin 8
(TSD) will read a nominal 0 V. Normal output of TSD is
typically equal to VDD.
If presented with a short duration transient such as a
lightning event, the thermal shutdown feature will
typically not activate. But in an extended power-cross
event, the device temperature will rise and the thermal
shutdown will activate forcing the switches to the all-off
R06
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