MAX121CAP 查看數據表（PDF） - Maxim Integrated

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MAX121CAP

308ksps ADC with DSP Interface and 78dB SINAD

Maxim Integrated 

MAX121

308ksps ADC with DSP Interface and 78dB SINAD

15

16

1

13

14

15

16

1

CLKIN

FSTRT

SCLK

15

16

(INVCLK = VCD)

SDATA LSB

HOLD

T/H

TRACK

1

13

14

15

16

MSB

D2

D1

LSB

tAQ

1

MSB

Figure 9. Continuous-Conversion Mode (Mode 3)

Applications Information

Initialization After Power-Up

Upon power-up, the first conversion of the MAX121 will be

valid if the following conditions are met:

1) Allow 16 clock cycles for the internal T/H to enter the

track mode, plus a minimum of 400ns in the track

mode for the data-acquisition time.

2) Make sure the reference voltage has settled. Allow

0.5ms for each 1µF of reference bypass capacitance

11ms for a 22µF capacitor.

Clock and Control Synchronization

If the clock and conversion start inputs (CONVST or CS—

see the Operating Modes section) are not synchronized,

the conversion time can vary from 15 to 16 clock cycles.

The SAR always changes state on the rising edge of

the CLKIN input. To ensure a fixed conversion time, see

Figure 10 and the following guidelines.

For a conversion time of 15 clock cycles, the conversion

start input(s) should go low at least 50ns before the next

rising edge of CLKIN. For a conversion time of 16 clock

CONVST OR CS

ICK

CLKIN

THE TIMING RELATIONSHIP BETWEEN CLKIN AND CONVST OR CS DETERMINES IF A

CLOCK CYCLE SLIPS OR NOT. USE THE FOLLOWING:

IF tCK < 10ns, CONVERSION TIME = 16 CLOCK EDGES

IF tCK > 50ns, CONVERSION TIME = 15 CLOCK EDGES

IF 10ns < tCK < 50ns, CONVERSION TIME IS INDETERMINATE (15 OR 16)

Figure 10. Clock and Control Synchronization

cycles, the conversion start input(s) should go low within

10ns of the next rising edge of CLKIN. If the conversion

start input(s) go low from 10ns of the next rising edge of

CLKIN. If the conversion start input(s) go low from 10ns

to 50ns before the next rising edge of CLKIN, the number

of clock cycles required is undefined and can be either 15

or 16. For best analog performance, the conversion start

inputs must be synchronized with CLKIN.

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