CDB4923 查看數據表（PDF） - Cirrus Logic

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CDB4923

Multi-Channel Digital Audio Decoders

Cirrus Logic 

CS4923/4/5/6/7/8/9

SWITCHING CHARACTERISTICS—MOTOROLA® HOST MODE

(TA = 25 °C; VA, VD = 3.3 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)

Parameter

Symbol

Min

Max

Unit

Address setup before CS and DS low

Tmas

5

-

ns

Address hold time after CS and DS low

Delay between DS then CS low or CS then DS low

Tmah

5

Tmcdr

0

-

ns

∞

ns

Data valid after CS and DS low with R/W high

Tmdd

-

20

ns

CS and DS low for read

(Note 3) Tmrpw

DCLK + 10

-

ns

Data hold time after CS or DS high after read

Tmdhr

5

-

ns

Data high-Z after CS or DS high low after read

(Note 4) Tmdis

-

15

ns

CS or DS high to CS and DS low for next read

(Note 3) Tmrd

2*DCLK + 10

-

ns

CS or DS high to CS and DS low for next write

(Note 3) Tmrdtw 2*DCLK + 10

-

ns

Delay between DS then CS low or CS then DS low

Tmcdw

0

∞

ns

Data setup before CS or DS high

Tmdsu

20

-

ns

CS and DS low for write

(Note 3) Tmwpw

DCLK + 10

-

ns

R/W setup before CS or DS low

Tmrwsu

5

-

ns

R/W hold time after CS or DS high

Tmrwhld

5

-

ns

Data hold after CS or DS high

Tmdhw

5

-

ns

CS or DS high to CS and DS low with R/W high for next read Tmwtrd 2*DCLK + 10

-

ns

(Note 3)

CS or DS high to CS and DS low for next write

(Note 3) Tmwd

2*DCLK + 10

-

ns

Notes: 3. Certain timing parameters are normalized to the DSP clock, DCLK, in nanoseconds. The DSP clock can

be defined as follows:

External CLKIN Mode:

DCLK == CLKIN/3 before and during boot

DCLK == CLKIN after boot

Internal Clock Mode:

DCLK == 10MHz before and during boot, i.e. DCLK == 100ns

DCLK == 60 MHz after boot, i.e. DCLK == 16.7ns (this speed may depend on CLKIN, please see

CS4923/4/5/6/7/8/9 Hardware Users Guide for more information)

4. This specification is characterized but not production tested.

10

DS262F2

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