CS5466 查看數據表（PDF） - Cirrus Logic

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CS5466

Low-cost Power/Energy IC with Pulse Output

Cirrus Logic 

CS5466

DIGITAL CHARACTERISTICS (Note 7)

• Min / Max characteristics and specifications are guaranteed over all operating conditions.

• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.

• VA+ = 5 V ±5% VD+ = 3.3 V ±5% or 5 V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.

• MCLK = 4.096 MHz

Parameter

Symbol

Master Clock Characteristics

Master Clock Frequency

Internal Gate Oscillator MCLK

Master Clock Duty Cycle

-

CPUCLK Duty Cycle

(Note 8 and 9)

-

Filter Characteristics

High-pass Filter Corner Frequency

-3 dB

-

Input/Output Characteristics

High-level Input Voltage

VIH

XIN

RESET

Low-level Input Voltage (VD = 5 V)

VIL

XIN

RESET

Low-level Input Voltage (VD = 3.3 V)

VIL

XIN

RESET

High-level Output Voltage (except XOUT)

Iout = +5 mA VOH

Low-level Output Voltage (except XOUT)

Iout = -5 mA VOL

Input Leakage Current

Iin

Digital Output Pin Capacitance

Cout

Drive Current FOUT, E1, E2, NEG

(Note 10) IDR

Min

Typ

3

4.096

40

-

40

-

-

0.125

(VD+) - 0.5 -

0.8 VD+

-

-

-

-

-

-

-

-

-

(VD+) - 1.0 -

-

-

-

±1

-

5

-

50

Max

5

60

60

-

-

-

1.5

0.2 VD+

0.3

0.2 VD+

-

0.4

±10

-

-

Unit

MHz

%

%

Hz

V

V

V

V

V

V

V

V

µA

pF

mA

Notes: 7.

8.

9.

10.

All measurements performed under static conditions.

If external MCLK is used, then the duty cycle must be between 45% and 55% to maintain this specification.

The frequency of CPUCLK is equal to MCLK.

VOL and VOH are not specified under this condition.

DS659F1

7

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