CS5541 查看數據表（PDF） - Cirrus Logic

零件编号

产品描述 (功能)

生产厂家

CS5541

Low-Power, Low-Voltage, 24-Bit ∆Σ ADC

Cirrus Logic 

CS5541

SWITCHING CHARACTERISTICS (TA = 25 °C; VA+ = +3.0 V ±5% VA- = 0 V, VD+ = 3.0 V ±5%,

DGND = 0 V; Input Levels: Logic 0 = 0 V, Logic 1 = VD+; CL = 50 pF)

Parameter

Symbol Min Typ Max Units

Master Clock Frequency:

Master Clock Duty Cycle

Rise Times

Fall Times

Start-up

Oscillator Start-up Time

Power-on-Reset Period

External Clock MCLK

Internal Oscillator (Note 20)

(Note 21) trise

Any Digital Input Except SCLK

SCLK

Any Digital Output

(Note 21) trise

Any Digital Input Except SCLK

SCLK

Any Digital Output

XTAL = 32.768 kHz (Note 22) tost

tpor

Serial Port Timing

Serial Clock Frequency

Serial Clock

SDI Write Timing

CS Enable to SCLK Rising

Data Set-up Time prior to SCLK rising

Data Hold Time After SCLK Rising

SCLK Falling Prior to CS Disable

SDO Read Timing

CS to Data Valid

SCLK Falling to New Data Bit

CS Rising to SDO Hi-Z

SCLK

Pulse Width High t1

Pulse Width Low t2

t3

t4

t5

t6

t7

t8

t9

5

-

40 kHz

- 32.768 -

40

-

60

%

-

-

1.0 µs

-

-

100 µs

-

50

-

ns

-

-

1.0 µs

-

-

100 µs

-

50

-

ns

-

500

-

ms

-

490

- MCLK

cycles

0

-

250

-

250

-

2 MHz

-

ns

-

ns

50

-

50

-

100

-

100

-

-

ns

-

ns

-

ns

-

ns

-

-

150 ns

-

-

150 ns

-

-

150 ns

Notes: 20. Device parameters are specified with 32.768 kHz clock; however, clocks up to 40 kHz can be used for

increased throughput.

21. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.

22. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an

external clock source.

8

DS500PP1

Share Link: