CS8406-CS 查看數據表（PDF） - Cirrus Logic
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CS8406-CS Datasheet PDF : 43 Pages
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CS8406
SWITCHING CHARACTERISTICS
(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)
Parameter
RST pin Low Pulse Width
OMCK Frequency for OMCK = 512*Fs
OMCK Low and High Width for OMCK = 512*Fs
OMCK Frequency for OMCK = 384*Fs
OMCK Low and High Width for OMCK = 384*Fs
OMCK Frequency for OMCK = 256*Fs
OMCK Low and High Width for OMCK = 256*Fs
OMCK Frequency for OMCK = 128*Fs
OMCK Low and High Width for OMCK = 128*Fs
Frame Rate
AES3 Transmitter Output Jitter
Symbol Min Typ Max Units
200
-
-
µs
4.1
-
98.4 MHz
4.1
-
-
ns
3.1
-
73.8 MHz
6.1
-
-
ns
2.0
-
49.2 MHz
8.1
-
-
ns
1.0
-
24.6 MHz
18.3
-
-
ns
8
-
192
kHz
-
200
-
ps
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)
Parameter
Symbol Min Typ Max Units
SDIN Setup Time Before ISCLK Active Edge
SDIN Hold Time After ISCLK Active Edge
Master Mode
OMCK to ISCLK active edge delay
OMCK to ILRCK delay
ISCLK and ILRCK Duty Cycle
(Note 5)
tds
10
-
-
ns
(Note 5)
tdh
8
-
-
ns
(Note 5) tsmd
(Note 6)
tlmd
0
-
17
ns
0
-
16
ns
-
50
-
%
Slave Mode
ISCLK Period
tsckw
36
-
-
ns
ISCLK Input Low Width
tsckl
14.4
-
-
ns
ISCLK Input High Width
tsckh
14.4
-
-
ns
ISCLK Active Edge to ILRCK Edge
(Note 7) tlrckd
10
-
-
ns
ILRCK Edge Setup Before ISCLK Active Edge
(Note 8) tlrcks
10
-
-
ns
Notes: 5. The active edge of ISCLK is programmable in Software mode.
6. The polarity of ILRCK is programmable in Software mode.
7. Prevents the previous ISCLK edge from being interpreted as the first one after ILRCK has changed.
8. This setup time ensures that this ISCLK edge is interpreted as the first one after ILRCK has changed.
DS580F1
7
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