CS8147 查看數據表（PDF） - ON Semiconductor

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CS8147

10 V/5.0 V Low Dropout Dual Regulator with ENABLE

ON Semiconductor 

CS8147

APPLICATION NOTES

Since both outputs are controlled by the same ENABLE,

the CS8147 is ideal for applications where a sleep mode is

required. Using the CS8147, a section of circuitry such as a

display and nonessential 5.0 V circuits can be shut down

under microprocessor control to conserve energy.

The test applications circuit diagram shows an automotive

radio application where the display is powered by 10 V from

VOUT1 and the Tuner IC is powered by 5.0 V from VOUT2.

Neither output is required unless both the ignition and the

Radio On/OFF switch are on.

Stability Considerations

The secondary output VOUT2 is inherently stable and does

not require a compensation capacitor. However a

compensation capacitor connected between VOUT1 and

ground is required for stability in most applications.

The output or compensation capacitor helps determine

three main characteristics of a linear regulator: start–up

delay, load transient response and loop stability.

The capacitor value and type should be based on cost,

availability, size and temperature constraints. A tantalum or

aluminum electrolytic capacitor is best, since a film or

ceramic capacitor with almost zero ESR can cause

instability. The aluminum electrolytic capacitor is the least

expensive solution, but, if the circuit operates at low

temperatures (–25°C to –40°C), both the value and ESR of

the capacitor will vary considerably. The capacitor

manufacturers data sheet usually provides this information.

The value for the output capacitor C2 shown in the test and

applications circuit should work for most applications,

however it is not necessarily the optimized solution.

To determine acceptable value for C2 for a particular

application, start with a tantalum capacitor of the

recommended value and work towards a less expensive

alternative part.

Step 1: Place the completed circuit with a tantalum

capacitor of the recommended value in an environmental

chamber at the lowest specified operating temperature and

monitor the outputs with an oscilloscope. A decade box

connected in series with the capacitor will simulate the

higher ESR of an aluminum capacitor. Leave the decade box

outside the chamber, the small resistance added by the

longer leads is negligible.

Step 2: With the input voltage at its maximum value,

increase the load current slowly from zero to full load while

observing the output for any oscillations. If no oscillations

are observed, the capacitor is large enough to ensure a stable

design under steady state conditions.

Step 3: Increase the ESR of the capacitor from zero using the

decade box and vary the load current until oscillations

appear. Record the values of load current and ESR that cause

the greatest oscillation. This represents the worst case load

conditions for the regulator at low temperature.

Step 4: Maintain the worst case load conditions set in step

3 and vary the input voltage until the oscillations increase.

This point represents the worst case input voltage

conditions.

Step 5: If the capacitor is adequate, repeat steps 3 and 4 with

the next smaller valued capacitor. A smaller capacitor will

usually cost less and occupy less board space. If the output

oscillates within the range of expected operating conditions,

repeat steps 3 and 4 with the next larger standard capacitor

value.

Step 6: Test the load transient response by switching in

various loads at several frequencies to simulate its real

working environment. Vary the ESR to reduce ringing.

Step 7: Raise the temperature to the highest specified

operating temperature. Vary the load current as instructed in

step 5 to test for any oscillations.

Once the minimum capacitor value with the maximum

ESR is found for each output, a safety factor should be added

to allow for the tolerance of the capacitor and any variations

in regulator performance. Most good quality aluminum

electrolytic capacitors have a tolerance of ±20% so the

minimum value found should be increased by at least 50%

to allow for this tolerance plus the variation which will occur

at low temperatures. The ESR of the capacitors should be

less than 50% of the maximum allowable ESR found in step

3 above.

Calculating Power Dissipation in a

Dual Output Linear Regulator

The maximum power dissipation for a dual output

regulator (Figure 16) is

PD(max) + NJVIN(max) * VOUT1(min)NjIOUT1(max) )

NJVIN(max) * VOUT2(min)NjIOUT2(max) ) VIN(max)IQ (1)

where:

VIN(max) is the maximum input voltage,

VOUT1(min) is the minimum output voltage from VOUT1,

VOUT2(min) is the minimum output voltage from VOUT2,

IOUT1(max) is the maximum output current, for the

application,

IOUT2(max) is the maximum output current, for the

application, and

IQ is the quiescent current the regulator consumes at

IOUT(max).

Once the value of PD(max) is known, the maximum

permissible value of RΘJA can be calculated:

RQJA

+

150°C *

PD

TA

(2)

The value of RΘJA can be compared with those in the

package section of the data sheet. Those packages with

RΘJA’s less than the calculated value in equation 2 will keep

the die temperature below 150°C.

In some cases, none of the packages will be sufficient to

dissipate the heat generated by the IC, and an external

heatsink will be required.

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