CDB8420 查看數據表（PDF） - Cirrus Logic

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CDB8420

Digital Audio Sample Rate Converter

Cirrus Logic 

CS8420

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ MODE

Inputs: Logic 0 = 0 V, Logic 1 = VD+; CL = 20 pF.

Parameter

Symbol Min Typ Max

CCLK Clock Frequency

CS High Time Between Transmissions

CS Falling to CCLK Edge

CCLK Low Time

CCLK High Time

CDIN to CCLK Rising Setup Time

CCLK Rising to DATA Hold Time

CCLK Falling to CDOUT Stable

Rise Time of CDOUT

Fall Time of CDOUT

Rise Time of CCLK and CDIN

Fall Time of CCLK and CDIN

(Note 13)

fsck

0

-

6.0

tcsh

1.0

-

-

tcss

20

-

-

tscl

66

-

-

tsch

66

-

-

tdsu

40

-

-

(Note 14)

tdh

18

-

-

tpd

-

-

45

tr1

-

-

25

tf1

-

-

25

(Note 15)

tr2

-

-

100

(Note 15)

tf2

-

-

100

Units

MHz

μs

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

13. If Fso or Fsi is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fso and

less than 128 Fsi. This is dictated by the timing requirements necessary to access the Channel Status and

User Bit buffer memory. Access to the control register file can be carried out at the full 6 MHz rate. The

minimum allowable input sample rate is 8 kHz, so choosing CCLK to be less than or equal to 1.024 MHz

should be safe for all possible conditions.

14. Data must be held for sufficient time to bridge the transition time of CCLK.

15. For fsck < 1 MHz.

CS

t css

t scl t sch

t csh

CCLK

t r2

t f2

CDIN

CDOUT

t dsu

t dh

t pd

Figure 3. SPI Mode Timing

10

DS245F4

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