CX06833-3 查看數據表（PDF） - Conexant Systems

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CX06833-3

SMXXD Modem

Conexant Systems 

CX06833-3x/4x SMXXD Modem Data Sheet

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Transmitter Holding Register Empty (THRE) [TX Buffer Empty].

This bit, when set, indicates that the TX Buffer is empty and the modem can

accept a new character for transmission. In addition, this bit causes the modem

to issue an interrupt to the host when the Transmit Holding Register Empty

Interrupt Enable bit (IIR1) is set to 1. The THRE bit is set to a 1 when a

character is transferred from the TX Buffer. The bit is reset to 0 when a byte is

written into the TX Buffer by the host.

In the FIFO mode, this bit is set when the TX FIFO is empty; it is cleared when

at least one byte is in the TX FIFO.

Break Interrupt (BI).

This bit is set to a 1 whenever the received data input is a space (logic 0) for

longer than two full word lengths plus 3 bits. The BI bit is reset when the host

reads the LSR.

Framing Error (FE).

This bit indicates that the received character did not have a valid stop bit. The

FE bit is set to a 1 whenever the stop bit following the last data bit or parity bit

is detected as a logic o (space). The FE bit is reset to a 0 when the host reads the

LSR.

In the FIFO mode, the error indication is associated with the particular character

in the FIFO it applies to; the FE bit is set to a 1 when this character is loaded

into the RX Buffer.

Parity Error (PE).

This bit indicates that the received data character in the RX Buffer does not have

the correct even or odd parity, as selected by the Even Parity Select bit (LCR4)

and the Stick Parity bit (LCR5). The PE bit is reset to a 0 when the host reads

the LSR.

In the FIFO mode, the error indication is associated with the particular character

in the it applies to; the PE bit is set to a 1 when this character is loaded into the

RX Buffer.

Overrun Error (OE).

This bit is set to a 1 whenever received data is loaded into the RX Buffer before

the host has read the previous data from the RX Buffer. The OE bit is reset to a

0 when the host reads the LSR.

In the FIFO mode, if data continues to fill beyond the trigger level, an overrun

condition will occur only if the RX FIFO is full and the next character has been

completely received.

Receiver Data Ready (DR).

This bit is set to a 1 whenever a complete incoming character has been received

and has been transferred into the RX Buffer. The DR bit is reset to a 0 when the

host reads the RX Buffer.

In the FIFO mode, the DR bit is set when the number of received data bytes in

the RX FIFO equals or exceeds the trigger level specified in FCR0-FCR1.

5-8

Conexant

102228A

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