5.3.2
5.4
5.4.1
CX06833-3x/4x SMXXD Modem Data Sheet
Receiver Character Timeout Interrupts
When the FIFO mode is enabled (FCR0 = 1) and receiver interrupt (Receiver Data
Available) is enabled (IER0 = 1), receiver character timeout interrupt operation is as
follows:
1. A Receiver character timeout interrupt code (IIR0-IIR3 = Ch) is set if at least one
received character is in the RX FIFO, the most recent received serial character was
longer than four continuous character times ago (if 2 stop bits are specified, the
second stop bit is included in this time period), and the most recent host read of the
RX FIFO was longer than four continuous character times ago.
Transmitter FIFO Interrupt Operation
Transmitter Empty Interrupt
When the FIFO mode is enabled (FCR0 = 1) and transmitter interrupt (TX Buffer Empty)
is enabled (IER0 = 1), transmitter interrupt operation is as follows:
1. The TX Buffer Empty interrupt code (IIR0-IIR3 = 2h) will occur when the TX
Buffer is empty; it is cleared when the TX Buffer is written to (1 to 16 characters) or
the IIR is read.
2. The TX Buffer Empty indications will be delayed 1 character time minus the last
stop bit time whenever the following occur: THRE = 1 and there have not been at
least two bytes at the same time in the TX FIFO Buffer since the last setting of
THRE was set. The first transmitter interrupt after setting FCR0 will be immediate.
102228A
Conexant
5-11