CXK5V8257BM 查看數據表（PDF） - Sony Semiconductor
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CXK5V8257BM Datasheet PDF : 9 Pages
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CXK5V8257BTM/BYM/BM
• Read cycle (WE = “H”)
-70LL
-10LL
Item
Symbol
Unit
Min. Max. Min. Max.
Read cycle time
tRC
70
—
100
— ns
Address access time
tAA
—
70
—
100 ns
Chip enable access time (CE)
tCO
—
70
—
100 ns
Output enable to output valid
tOE
—
35
—
50 ns
Output hold from address change
tOH
20
—
20
— ns
Chip enable to output in low Z (CE)
tLZ
10
—
10
— ns
Output enable to output in low Z (OE) tOLZ
5
—
10
— ns
Chip disable to output in high Z (CE) tHZ∗1
—
30
—
35 ns
Output disable to output in high Z (OE) tOHZ∗1 —
30
—
35 ns
∗1 tHZ and tOHZ are defined as the time required for outputs to turn to high impedance state and are not
referred to as output voltage levels.
• Write cycle
Item
Write cycle time
Address valid to end of write
Chip enable to end of write
Data to write time overlap
Data hold from write time
Write pulse width
Address setup time
Write recovery time (WE)
Write recovery time (CE)
Output active from end of write
Write to output in high Z
Symbol
tWC
tAW
tCW
tDW
tDH
tWP
tAS
tWR
tWR1
tOW
tWHZ∗2
-70LL
Min. Max.
70
—
60
—
60
—
30
—
0
—
55
—
0
—
0
—
0
—
10
—
—
30
-10LL
Unit
Min. Max.
100
— ns
80
— ns
80
— ns
35
— ns
0
— ns
60
— ns
0
— ns
0
— ns
0
— ns
10
— ns
—
35 ns
∗2 tWHZ is defined as the time required for outputs to turn to high impedance state and is not referred to as
output voltage level.
–4–
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