CXL1506N 查看數據表（PDF） - Sony Semiconductor
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CXL1506N Datasheet PDF : 12 Pages
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CXL1506M/N
Pin Description (CXL1506N)
Pin No.
Symbol
I/O
Description
1
NC
—
—
2
IN
I
Signal input
(Non-inverted signal)
3
VG1
4(Note) VG2
O Gate bias 1 DC output
I Gate bias 2 DC input
Impedance [Ω]
> 10kΩ (at no clamp)
5
OUT1
6
VSS
7
OUT2
O
1H signal output
(Inverted signal)
— GND
O
2H signal output
(Inverted signal)
40 to 500Ω
40 to 500Ω
8
NC
—
—
9
VSS (VCO OUT) (O) GND or VCO output (3fsc)
10
VSS
— GND
11
VDD
— Power supply (5V)
12 CLK
I Clock input (fsc)
> 10kΩ
13 NC
—
—
14
VSS
— GND
15 PC OUT
O Phase comparator output
16 VCO IN
I VCO input
17
VDD
— Power supply (5V)
18 AB
O Autobias DC output
600 to 200kΩ
19 NC
—
—
20
VSS
— GND
Note) Description of VG2
Control of input signal clamp condition
0V … Sync tip clamp condition
5V … Center bias condition
The input signal is biased to approx. 2.1V by means of the IC internal resistance (approx. 10kΩ ).
In this mode the input signal is limited to the APL 50% and the maximum input signal amplitude is
at 200mVp-p.
–3–
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