CXL1506N 查看數據表（PDF） - Sony Semiconductor

零件编号

产品描述 (功能)

生产厂家

CXL1506N

CMOS-CCD 1H/2H Delay Line for PAL

Sony Semiconductor 

CXL1506M/N

6) The noise level of the output signal at no-input signal is tested with a video noise meter in the Sub Carrier

Trap mode at BPF 100kHz to 5MHz. (Vn [Vrms])

The signal component is determined either by testing the output voltage (the same testing system as for

noise level) at the input of 350mVp-p, 200kHz, or by utilizing values from GL to calculate according to the

following formula. (Vs [Vp-p])

(Example of Vs calculation)

GL

Vs = 0.35 × 10 20

(Example of SN ratio calculation)

SN = 20 log Vn (noise component) [Vrms] [dB]

Vs (signal component) [Vp-p]

7) The internal clock component to the output signal during no-signal input and the leakage of that high

harmonic component are tested.

Test value [mVp-p]

Clock

400mVp-p

(typ.)

fsc (4.433619MHz) sine wave

–7–

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