CY14B101K 查看數據表（PDF） - Cypress Semiconductor

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CY14B101K

1 Mbit (128K x 8) nvSRAM With Real Time Clock

Cypress Semiconductor 

CY14B101K

When an enabled interrupt source activates the INT pin, an

external host can READ the Flags or Control registers to

determine the cause. Remember that all flags are cleared when

the register is READ. If the INT pin is programmed for Level

mode, then the condition clears and the INT pin returns to its

inactive state. If the pin is programmed for Pulse mode, then

reading the flag also clears the flag and the pin. The pulse does

not complete its specified duration if the Flags or Control

registers are READ. If the INT pin is used as a host reset, then

the Flags or Control registers must not be READ during a reset.

During a power on reset with no battery, the Interrupt register is

automatically loaded with the value 24h. This enables power fail

interrupt with an active LOW pulse.

Flags Register – The Flags register has three flag bits: WDF,

AF, and PF. These flag bits are initialized to 00h. These flags are

set by the watchdog timeout, alarm match, or power fail monitor,

respectively. The processor either polls this register or enables

to inform interrupts when a flag is set. The flags are automatically

reset once the register is READ.

Figure 5. RTC Recommended Component Configuration

Recommended Values

Y1 = 32.768 KHz

RF = 10 MΩ

C1 = 0

C2 = 56 pF

Watchdog

Timer

Power

Monitor

VINT

Figure 6. Interrupt Block Diagram

WDF

WIE

PF

PFE

Clock

Alarm

AF

AIE

Legend

WDF - Watchdog Timer Flag

WIE - Watchdog Interrupt Enable

PF - Power F ail Flag

PFE - Power Fail Enable

AF - Alarm Flag

AIE - Alarm Interrupt Enable

P/L - Pulse Level

H/L - High/Low

P/L

Pin

Driver

H/L

VCC

VSS

Document Number: 001-06401 Rev. *G

INT

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